Hack the Wire with Ciena

📅 January, 2026

⏰ Afternoon Event

⚙ Design Challenge | In Person

Join Ciena FPGA engineers for a hands-on design challenge and networking session. Ciena will present a surprise real-world problem, and teams will spend the afternoon programming creative FPGA-based solutions. Expect prizes, mentorship, and the chance to connect directly with industry engineers.

Synopsys Networking & Information Session

📅 September 24th, 2025

⏰ TBD

⚙ In Person | Industry Panel

Engineers from Synopsys joined us on campus to share insights into digital design in industry. The session featured a panel discussion, Q&A, and one-on-one networking with students interested in hardware and chip design.

Intro to Verilog

📅 September 10, 2025

⏰ TBD

🧰 Beginner | Hybrid

Learn the basics of hardware description using Verilog in this introductory session.