Current Projects
Custom FPGA Communication Protocol
This project designs a full-duplex FPGA-to-FPGA communication system enabling [cite_start]reliable bidirectional data transfer[cite: 9]. The architecture incorporates 8b/10b [cite_start]line encoding, data scrambling, and cyclic redundancy check (CRC) for error detection[cite: 10]. It features master-initiated link initialization and explicit Clock Domain Crossing (CDC) [cite_start]protection, ensuring compatibility between FPGAs with independent clock sources[cite: 11, 12].
Join the DiscordVector Processing Unit (VPU)
The VPU Team is building a scalable Vector Processing Unit in Verilog, featuring a custom ALU capable of vector addition, subtraction, multiplication, and dot products. The design supports 32-bit signed vector elements and modular arithmetic components.
Join the DiscordEmulator Team
The Emulator Team is developing a custom 32-bit RISC-V (RV32I) CPU from scratch in SystemVerilog. The ultimate goal is to integrate the CPU into a retro-style FPGA game console capable of running simple 8-bit and 16-bit games like Pong or Tetris.
Join the DiscordStart Your Own Project
Do you have an idea for a hardware design, a new protocol, or an embedded system? We are always looking for new initiatives. Submit a proposal to lead your own team.
Project Proposal Form